The present invention relates to method of manufacturing a semiconductor device, and more particularly, a dynamic random access memory (DRAM) having a stacked capacitor.
Conventionally, the DRAM comprises a plurality of memory cells. In each memory is stored the respective data. The memory cell consists of a cell transistor and a capacitor having a storage electrode.
Recently, such a memory has been highly integrated. However, the reduction of capacity of the storage electrode is undesirable from the viewpoint of the confidence of the data stored in a capacitor. Therefore, it is both important and a problem to secure the capacity of a memory cell.
To satisfy the demand, there has been proposed a stacked capacitor wherein a storage electrode is provided on a cell transistor. It is an aim of using a stacked capacitor to secure capacity by the height of the stacked storage electrode.
Such a memory having a stacked storage electrode is disclosed in Japanese Laid-Open (kokai) Patent Publication No. 5-226583 and will be described with reference to FIGS. 1A-1G.
As shown in FIG. 1A, a field oxide film 105 is formed on a p-type silicon substrate 101 and gate electrodes 104 are selectively formed through the respective gate insulating film 103 on the silicon substrate 101. Thereafter, n.sup.+ diffused layers 102 are formed within the surface region of the substrate 101 to form a source-drain region of a MOS transistor. The gate electrode 104 serves as a word line of a DRAM. An SiO.sub.2 layer is deposited on the MOS transistor by a CVD method to thereby form a first interlayer insulating film 106. Boron-phosphorus doped silicate glass (BPSG) film is then deposited by a CVD method to a thickness of 100 nm, to thereby form a second interlayer insulating film 107a. A heating reflow is conducted on the entire surface to form a flat surface and the BPSG film is etched-back by a reactive ion etching, or RIE, method to thereby form a second interlayer insulating film 107b having a thickness of 500 nm as shown in FIG. 1B.
As shown in FIG. 1C, a contact hole 108 is formed in the first and second interlayer insulating film 106 and 107b to expose the n.sup.+ diffused layer 102 by using a photolithographic technique. A poly-crystal silicon 109a is deposited on the second interlayer insulating film 107b and in the contact hole 108 to a thickness of 250 nm. After an etching mask is formed on a portion including the contact region (not shown), the poly-crystal silicon 109a is patterned by an anisotropic etching method to thereby form a pattered silicon film 109. Using the etching mask as a mask again, the second interlayer insulating film 107b is anisotropically etched to thereby provide the etched BPSG film having a thickness of 300 nm.
As a result, as shown in FIG. 1D, the second interlayer insulating film 107b under the patterned silicon film 109 is thicker than that not under the patterned silicon film 109.
Next, as shown in FIG. 1E, a thin film poly-silicon film 110a is deposited by a CVD method to a thickness of 150 nm.
As shown in FIG. 1F, the thin film poly-silicon film 110a is etched-back by an RIE method to produce sidewalls 110. The sidewalls 110 is electrically connected to the patterned silicon film 109 so that the side walls 110 and the patterned silicon film 109 function as a first (under) electrode of a capacitor.
Next, a storage electrode insulating film 111 is deposited on the entire surface and a poly-silicon film is deposited on the storage electrode insulating film 111. The polysilicon film are then patterned by a photolithographic technique to thereby produce a second (upper) electrode 112. At this time, the storage electrode insulating film 111 is patterned, as well. An interlayer insulating film 113 is deposited to a thickness of 400 nm. A contact hole is then formed in the interlayer insulating film 113 to expose or reach the n.sup.+ diffused layer 102 by a photolithographic technique. Thereafter, an aluminum film is deposited to produce a bit line 114. As a result, a conventional DRAM cell having a stacked storage capacitor is provided as shown in FIG. 1G.
The capacitor consisting of the memory cell has the first electrode having the patterned silicon film 109 and sidewalls 110. The first electrode covers the top and both side faces of the second interlayer insulating film 107b under the first electrode. Therefore, the structure prevents the first electrode of the capacitor from falling or peeling off since the first electrode of the capacitor is firmly maintained by the shape or connection relation of the first electrode and the second interlayer insulating film 107b.
However, In the case of a more miniaturized DRAM of not less than 256 Mb memory, it becomes more difficult for data stored in the above-mentioned capacitor to be secured reliablely.